1. Field of the Invention
A high input impedance common-emitter amplifier stage.
2. Background of the Related Art
Low power operational amplifiers with a rail to rail output stage are designed with the goal of maintaining a high open loop gain while driving heavy output loads. Since the output of a rail-to-rail amplifier has to swing all the way to the supply rails, the classical class-AB voltage follower buffer implemented with emitter followers cannot be used. Instead, the push-pull transistors must be configured in a common-emitter configuration. In addition, this stage must provide high voltage gain because the addition of another gain stage complicates the task of frequency compensation of the amplifier.
A simplified schematic of a conventional amplifier circuit with a rail-to rail output is shown in FIG. 1. This conventional amplifier circuit comprises two NPN transistors Q1 and Q2, arranged in a Darlington configuration. The circuit also comprises an PNP transistor Q3, which provides a rail-to-rail output. The base of Q1 is driven by the input transconductance stage GM, while the base of Q3 is driven by PNP drive and bias circuitry. Current source I1 biases Q1 to maintain a minimum current through Q1 and to minimize phase shift. Such a conventional circuit is disadvantageous because the input impedance of the Darlington common-emitter stage limits the open loop gain of the circuit. This is especially true when the amplifier is built in a high frequency process often characterized by low current gain (i.e., where the value of .beta. is low).
FIGS. 2 and 3 depict two other conventional techniques used to increase the input impedance of the Darlington stage. The circuit in FIG. 2 uses additional emitter-followers Q4 and Q5 to increase the input impedance of the circuit. Specifically, the circuit in FIG. 2 utilizes two transistors, Q4 and Q5 and two current sources I2 and I3, in addition to the Darlington configuration of FIG. 1. Current source I3 biases Q5 to maintain a minimum current through Q5 and to minimize phase shift. I3 also provides the base current for Q4. Current source I2 provides the bias current for Q4 and the base current for Q1. I1 biases Q1 to maintain a minimum current through Q1 and to minimize phase shift. A drawback of this technique is that the phase shift resulting from the use of additional emitter-followers reduces the phase margin of the circuit, especially when they are biased at low currents to minimize power dissipation.
The circuit in FIG. 3 uses base current cancellation to increase the input impedance. The circuit of FIG. 3 utilizes four transistors, Q4, Q5, Q6 and Q7 in addition to the Darlington configuration of FIG. 1. In this circuit, the current through Q4 is equal to the current through Q1 (assuming base currents are relatively low). It follows then that the base current of Q4 is substantially equal to the base current of Q1. The base current of Q4 is mirrored by Q5 to Q6, and as a result, the current through Q7 is also substantially equal to the base current of Q4 and thus of Q1. As a result, the base current of Q1 is mostly provided by Q7, effectively increasing the input impedance of the circuit. However, the cancellation technique provided by this circuit can only achieve a three to four-fold increase in input impedance due to dissimilar collector-base voltages of the cancellation transistors.
Accordingly, there is a need in the technology to provide a high input impedance common-emitter amplifier stage. There is a also a need in the technology to provide a circuit with a high input impedance common-emitter amplifier stage which can maintain identical collector-base voltages in the cancellation circuit.